The disclosed embodiments of the present invention relate to signal sampling, and more particularly, to a sampling circuit and a related control method capable of reducing mismatch sources between signal paths.
A time-interleaved architecture is traditionally used to realize a high speed and high resolution analog-to-digital converter (ADC). However, offset errors, gain errors, and timing skews may degrade the performance of the time-interleaved ADC. Compared to the offset errors and the gain errors, the timing skews are more difficult to reduce. Even though the amount of time it takes to transmit an input signal to each signal path (or each channel) is identical, devices in signal paths are unmatched due to process limitation.
One conventional method for reducing the timing skews is to use the master clock sampling technique. The device mismatch still occurs in the control logic of the master clock sampling. Thus, there is a need for a novel circuit design to solve the timing skew problem.